// =============================================================================
// Module Name: IPat_BsrBC_4.v
// Revision: 20220504a
// Author: Altmo toolbox
// Description:
//  + JTAG BSR type BC_4
// =============================================================================

`timescale 1ns/1ns

module IPat_BsrBC_4 (
    input  fi,       // input  for normal/user function
    
    input  si,       // BSR chain input
    output so,       // BSR chain output
    
    input  capture,  // BSR capture
    input  shift,    // BSR shift
    input  tck       // BSR clock
);

    parameter u_dly = 1; // unit delay for registers input
    
    reg r_capture; // BSR capture/shift-FF
    
    assign so = r_capture;
    
    wire w_capture;
    
    always @(posedge tck) begin
        r_capture <= #u_dly w_capture;
    end
    
    assign w_capture = (shift)?   si :
                       (capture)? fi : r_capture;
    
endmodule